1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a perspective view of an illustrative prior art integrated circuit product 100 that is formed above a semiconductor substrate 105. In this example, the product 100 includes five illustrative fins 110, 115, a shared gate structure 120, a sidewall spacer 125, and a gate cap 130. The product 100 implements two different FinFET transistor devices (N-type and P-type) with a shared gate structure. The gate structure 120 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the transistors on the product 100. The fins 110, 115 have a three-dimensional configuration. The portions of the fins 110, 115 covered by the gate structure 120 define the channel regions of the FinFET transistor devices on the product 100. An isolation structure 135 is formed between the fins 110, 115. The fins 110 are associated with a transistor device of a first type (e.g., N-type), and the fins 115 are associated with a transistor device of a complementary type (e.g., P-type). The gate structure 120 is shared by the N-type and P-type transistors, a common configuration for memory products, such as static random access memory (SRAM) cells.
Typically, fins are formed in a regular array. To define separate transistor devices, the length of the fins may be adjusted and some fins or portions of fins may be removed. For example, a fin cut or “FC cut” process cuts fins in the cross direction by removing fin portions inside the FC cut mask. An active region cut process, or “RX cut” process removes one or more of the fin segments in the parallel direction by removing fin portions located outside the RX cut mask. The FC cut mask exposes portions of the fins and the dielectric material disposed above and between the fin portions. An etch process forms a trench that removes the dielectric material and the fin portions. The FC cut process exposes end surfaces of the fins where the FC cuts are performed. The RX cut mask covers fin portions that are to be retained and exposes other fin portions that are to be removed. The dielectric material above the fin portions to be removed is removed to expose the underlying fin portions. A subsequent etch process removes the exposed fin portions. However, because some of the end surfaces of the fin portions that were previously exposed during the FC cut are still exposed during the fin removal etch, the end surfaces can be eroded or undercut by the RX cut, thereby damaging the associated fins or segments.
After performing the RX cut, the recesses created by removing the fins are typically filled with a liner material. This liner material also covers the exposed end surfaces, so that a low-k dielectric material can be formed and densified in the regions between the fins to create isolation regions without damaging the fins. The isolation regions are etched back to expose portions of the fins, however, due to the high aspect ratio of the recesses and the different material of the liner layer, the liner material is not easily removed. Typically, the liner layer has a higher dielectric constant than the isolation regions. The remaining portions of the liner layer increase the capacitance of the device, thereby reducing performance.
FIGS. 2A-2B are cross-section views of a device 200 showing a first fin segment 205A and a second fin segment 205B defined above a substrate 210. In FIGS. 2A-2B, the cross-section is taken through the long axis of the fin segments 205A, 205B. The fin segments 205A, 205B were formed by performing an FC cut to remove a portion of the longer fin 205, as described above, to define a trench 212. An oxide cap layer 215 and a nitride cap layer 220 (previously used as hard mask layers to pattern the fin 205 in the substrate 210) are present above the fin segment 205A. Liners 225, 230 are formed on ends and the sidewalls of the fin 205 prior to forming the trench 212 that separates the fin 205 into the fin segments 205A, 205B. After formation of the trench 212, the cap layers 215, 220 were selectively removed from the fin segment 205B so that the fin segment 205B can be removed during a subsequent RX cut process. The cap layers 215, 220 remain positioned above the fin segment 205A.
FIG. 2B illustrates the device 200 after the RX cut process was performed. Because the cut end surface 205E of the fin segment 205A is exposed, the isotropic RX cut etch process erodes the end surface 205E, thereby damaging the fin segment 205A.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.